The input/output buffer information specification (IBIS) was developed by Intel® Corporation in the early 1990s as a behavioral model that describes the electrical characteristics of the digital inputs and outputs of a device. Rather than using schematic symbols or polynomial expressions, an IBIS model instead consists of tabular data that contains current and voltage values for the input pins of the device, as well as the voltage/time relationships that exist at the output pins of the device under rising and/or falling switching conditions.
Since IBIS models describe the behavioral aspects of the inputs and outputs of a device through voltage/current (V/I) and voltage/time (V/T) data, disclosure of proprietary information, such as semiconductor process and circuit information, need not be disclosed within the IBIS models. As such, semiconductor vendors are no longer reluctant to release behavioral information about their devices, since the proprietary aspects of the devices may remain confidential, while the behavioral aspects of those devices may be released in support of the simulation platforms that are used to characterize performance of those devices.
Many electronic design automation (EDA) vendors support the IBIS specification due in large part to the accuracy of the IBIS model. In particular, non-linear aspects of the input/output (I/O) structures, the electrostatic discharge (ESD) structures, and the device package parasitics may all be represented within a typical IBIS model. IBIS also provides several advantages over traditional simulation models, such as HSPICE, since IBIS based simulations typically execute much faster than HSPICE based simulations. In addition, IBIS based models may be executed on industry-wide platforms since most EDA vendors support the IBIS specification.
IBIS models facilitate testing of I/O interfaces, verification at the board level, such as signal integrity and system level timing, and interoperation at the system level. Data used to generate the IBIS models may either be gathered from simulated circuit measurements, such as may be obtained using HSPICE, or gathered from bench measurements conducted on actual semiconductor devices. If a simulation is used, the V/I and V/T data for each of the I/O buffers may be generated by an HSPICE-to-IBIS (S2I) conversion program for each process corner, e.g., typical, weak (slow), and strong (fast), which are defined with respect to process, temperature, and supply variations. Once the V/I and V/T data for each of the I/O buffers is generated, the S2I conversion program also generates the raw IBIS model.
As I/O standards proliferate, however, so does the number of models that are needed to simulate them. For example, the I/O interface of a typical field programmable gate array (FPGA) may be configured to support several hundred I/O standards. Thus, in order to characterize the FPGA's performance over each I/O standard, one IBIS model must be created for each I/O standard. In addition, a correlation report must be generated to determine the accuracy of the IBIS model as compared to the transistor netlist counterpart that may be utilized during an HSPICE simulation. Thus, conventional techniques that may be used to generate IBIS models become cumbersome when tasked with producing IBIS models for multiple I/O standards.
Efforts continue, therefore, to automate IBIS model generation and correlation so as to expedite the modeling and simulation of multiple I/O standards.